1. Field of the Invention
The present invention relates to semiconductor devices and methods for inspecting and testing semiconductor devices and, more specifically, to BGA (ball grid array) semiconductor devices and inspection and test methods therefor.
2. Description of the Related Art
As semiconductor technology evolves, the complexity of the circuitry capable of being placed on a semiconductor chip increases while at the same time, the size of the semiconductor package decreases. In order to take full advantage of evolving semiconductor technology, the number of signal input/output (I/O) leads per chip must increase, requiring a reduction in spacing between adjacent peripheral I/O leads on the semiconductor device.
A quad-flat-pack (QFP) semiconductor device has been used for relatively low pin count surface mount applications. A QFP device can allow an outer lead pitch of 0.5 mm. Although some applications of QFP can allow for an outer lead pitch of 0.4 mm or even 0.3 mm, this generally results in a lower assembly yield. The body size of QFP devices is typically on the order of 28 mm or less, resulting in a peripheral I/O pin count far below that necessary in many applications.
FIGS. 9A-9C depict the operational flow of QFP devices being tested utilizing a conventional test setup. QFP devices 51 are initially prearranged in an insulated plastic tray 53 with their leads 52 positioned on the lower side, as shown in FIG. 9A. A DUT (device under test) board 55 having a socket 54 designed to accommodate QFP device 51, is situated on contact probes 57 provided on test head 56 (e.g., an electrical measurement and/or test device). Socket 54 has a plurality of electrical contacts (not shown) each corresponding to a lead 52 of QFP device 51. The electrical contacts include leads which extend to the bottom of DUT board 55, where additional contacts are provided, each corresponding to a contact probe 57. Contact probes 57 provide I/O signals between test head 56 and QFP device 51 under test. That is, the side of DUT board 55 opposite to which socket 54 is mounted, is electrically connected to test head 56 via contact probes 57.
Typically, utilizing automated equipment (not shown), a QFP device 51 is picked up and removed from tray 53 and placed into socket 54, as shown in FIG. 9B. The QFP device is then subjected to a predetermined series of electrical tests and/or measurements by test head 56. After the tests and/or measurements are completed, the tested QFP device is returned to a second tray 53', with the same side facing up, as shown in FIG. 9C.
Although such a QFP semiconductor device provides a sufficient number of peripheral I/O pins for many applications, as noted above, the maximum number of I/O pins is still far less than that necessary in many applications.
To provide a higher peripheral I/O contact count, a ball-grid-array (BGA) semiconductor device is often employed. The BGA semiconductor device allows an I/O pad or ball pitch, on the order of 1.5 mm for high I/O requirements, typically resulting in 225 I/O connection points (e.g., see Nikkei Electronics, Feb. 14, 1994, p60-p67).
FIGS. 7A and 7B show in cross-section and a top plan view, respectively, a typical BGA device. In the typical BGA device, semiconductor chip 32 is die-bonded to one side of substrate 31 utilizing a heat resistant bonding resin such as die-bonding epoxy plastic 37. Each electrical I/O connection of semiconductor chip 32 is electrically connected to a corresponding conductor pattern 41 (the shaded portion as shown in cross-section in FIG. 7A) via a bonding wire 33. Each conductor pattern 41 extends via a through-hole 34 to the opposite side of substrate 31 as shown. Solder resist 38 is provided on the device to electrically insulate and protect conductor patterns 41, and a molding resin 36 encapsulates semiconductor chip 32 and bonding wires 33. Solder balls 35 are formed on a bottom surface of the device and provide I/O connection points. Each conductor pattern 41 is electrically connected to a corresponding solder ball 35. Solder balls 35 thus form terminals that can be electrically connected to a test head or to a BGA socket for providing electrical signals to and from semiconductor chip 32.
Additional solder balls 40 may be provided in the central portion of the device for the transfer of heat to and from semiconductor chip 32. For example, through-holes 39 and conductor pattern 42 act as thermal piers for the transfer of thermal radiation (e.g., heat) from solder balls 40 to semiconductor chip 32 during a semiconductor heating process performed during chip testing. In addition, they also act as heat sinks to provide radiational cooling by transferring heat away from semiconductor chip 32 when the semiconductor chip is operating.
An inspection method is known according to which test pads are provided on the face of the printed-circuit board, opposite the area to which the BGA is mounted (Nikkei Electronics, Feb. 14, 1994, p68-p73). In another well-known method, which helps to facilitate inspection after mounting, a scan design method is utilized for an automatic testing process for ASICs (Nikkei Electronics, Mar. 20, 1989, P209-p216).
Utilizing conventional techniques to test the BGA package semiconductor device, it is necessary to electrically connect each I/O solder ball 35 to a test probe. Typically, this is accomplished by bringing a probe such as a pin 83 or a socket 81 (shown in FIGS. 8A and 8B) into contact with each solder ball. The probes may or may not be provided with a spring 82 for urging the probes toward the solder balls. Pressure is applied to the BGA package so that the solder balls are forced against the probes, to ensure positive electrical contact between the probes and the solder balls. However, this procedure can result in the generation of flaws such as dents or chips on the surfaces of the solder balls. For example, as shown in FIG. 8A, a socket probe 81 can be used to electrically connect each solder ball 35 of a BGA device to a specially designed test head. However, the solder forming the solder balls is typically a very soft material. Accordingly, when the BGA device is pressed down, urging solder balls 35 against socket probes 81, the solder balls may tend to deform as shown. As shown in FIG. 8B, if pin-type probes 83 are used, the solder balls may tend to dent or chip.
Such irregularities or flaws on the solder balls are unacceptable, since the solder balls are designed for mating with corresponding contacts in a BGA mounting socket. Accordingly, any irregularities or flaws on the solder balls may prevent good electrical contact from being made between the solder balls and the mounting socket contacts.
To perform comprehensive testing of a semiconductor device, the device is often heated to a predetermined temperature utilizing a heat plate and then subjected to additional electrical tests. Heating of a BGA device is conventionally performed by placing the BGA device on the heat plate with the solder balls on the heating surface. However, heating the semiconductor device in this manner is inefficient and time consuming. In addition, since the solder balls on a BGA device are arranged closely together, it is important that a visual inspection of the ball grid array be performed. However, such a visual inspection requires additional steps to be performed in the typical test procedure. For example, during electrical testing the BGA device is currently arranged on a test head socket with the solder ball side of the device face down on the test head. However, visual inspection of the ball grid array requires that the BGA device be flipped over or inverted to allow the surface of the semiconductor device having the solder balls to be viewed. This requires more test time per device and also requires more complex and costly automated equipment to invert the semiconductor device.